Expanded Noise Margin 10T SRAM Cell using Finfet Device
نویسندگان
چکیده
Static random access memory (SRAM) cells are being improved in order to increase resistance device level changes and satisfy the requirements of low-power applications. A unique 10-transistor FinFET-based SRAM cell with single-ended read differential write functionality is presented this study. This cutting-edge architecture more power-efficient than ST (Schmitt trigger) 10T or traditional 6T cells, using only 1.87 1.6 units power respectively during operations. The efficiency attributable a lower activity factor, which saves electricity. static noise margin (RSNM) (WSNM) proposed show notable improvements over cell, increasing by 1.67 1.86, respectively. Additionally, compared time has been significantly reduced 1.96 seconds. Utilising Cadence Virtuoso tool an 18nm Advanced Node Process Design Kit (PDK) technology file, design's efficacy confirmed. For electronic systems next-generation applications, exciting lot potential.
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ژورنال
عنوان ژورنال: International Journal on Recent and Innovation Trends in Computing and Communication
سال: 2023
ISSN: ['2321-8169']
DOI: https://doi.org/10.17762/ijritcc.v11i9s.7959